# A6.1
11101(:11)	IS_T32
11110(:11)	IS_T32
11111(:11)	IS_T32

# A6.2.5
1011(opcode:7)(:5)	{eq(band(opcode,0x70),0x30)} {ne(opcode,0x32)} {ne(opcode,0x33)}	UNDEFINED
1011(opcode:7)(:5)	{eq(band(opcode,0x78),0x40)}	UNDEFINED
1011(opcode:7)(:5)	{eq(band(opcode,0x7e),0x54)}	UNDEFINED
10111111(opA:4)(opB:4)	{gt(opA,4)} {lnot(opB)}	UNALLOCATED_HINT

# A8.8.2 ADC (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100000101(Rm:3)(Rdn:3)				ADC_reg_T1

# A8.8.4 ADD (imm, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0001110(imm3:3)(Rn:3)(Rd:3)			ADD_imm_T1
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
00110(Rdn:3)(imm8:8)				ADD_imm_T2

# A8.8.6 ADD (register, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0001100(Rm:3)(Rn:3)(Rd:3)			ADD_reg_T1
# T2 ARMv6T2, ARMv7
01000100(DN)(Rm:4)(Rdn:3)	{lnot(DN)} {lt(Rm,8)}	ADD_reg_T2a
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
01000100(DN)(Rm:4)(Rdn:3)	{lor(DN,ge(Rm,8))} {lor(ne(DN,1),ne(Rdn,5))} {ne(Rm,13)}	ADD_reg_T2b

# A8.8.9 ADD (SP plus immediate)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
10101(Rd:3)(imm8:8)				ADD_sp_imm_T1
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
101100000(imm7:7)				ADD_sp_imm_T2

# A8.8.10 ADD (SP plus register, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
01000100(DM)1101(Rdm:3)				ADD_sp_reg_T1
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
010001001(Rm:4)101		{ne(Rm,13)}	ADD_sp_reg_T2

# A8.8.12 ADR
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
10100(Rd:3)(imm8:8)		ADR_T1

# A8.8.14 AND (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100000000(Rm:3)(Rdn:3)		AND_reg_T1

# A8.8.14 ASR (immediate)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
00010(imm5:5)(Rm:3)(Rd:3)	ASR_imm_T1

# A8.8.17 ASR (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100000100(Rm:3)(Rdn:3)		ASR_reg_T1

# A8.8.18 B
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
1101(cond:4)(imm8:8)	{lt(cond,14)}	B_T1
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
11100(imm11:11)				B_T2

# A8.8.23 BIC (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100001110(Rm:3)(Rdn:3)			BIC_reg_T1

# A8.8.24 BKPT
# T1 ARMv5T*, ARMv6*, ARMv7
10111110(imm8:8)			BKPT_T1

# A8.8.26 BLX (register)
# T1 ARMv5T*, ARMv6*, ARMv7
010001111(Rm:4)(000)	BLX_reg_T1

# A8.8.27 BX
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
010001110(Rm:4)(000)	BX_T1

# A8.8.29 CBNZ, CBZ
# T1 ARMv6T2, ARMv7
1011(op)0i1(imm5:5)(Rn:3)	CBNZ_CBZ_T1

# A8.8.35 CMN (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100001011(Rm:3)(Rn:3)		CMN_reg_T1

# A8.8.37 CMP (immediate)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
00101(Rn:3)(imm8:8)		CMP_imm_T1

# A8.8.38 CMP (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100001010(Rm:3)(Rn:3)		CMP_reg_T1
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
01000101N(Rm:4)(Rn:3)		CMP_reg_T2

# A8.8.47 EOR (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100000001(Rm:3)(Rdn:3)	EOR_reg_T1

# A8.8.54 IT
# T1 ARMv6T2, ARMv7
10111111(firstcond:4)(mask:4)	{mask}	IT_T1

# A8.8.62 LDR (immediate, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
01101(imm5:5)(Rn:3)(Rt:3)	LDR_imm_T1
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
10011(Rt:3)(imm8:8)		LDR_imm_T2

# A8.8.64 LDR (literal)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
01001(Rt:3)(imm8:8)		LDR_lit_T1

# A8.8.65 LDR (register, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0101100(Rm:3)(Rn:3)(Rt:3)	LDR_reg_T1

# A8.8.67 LDRB (immediate, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
01111(imm5:5)(Rn:3)(Rt:3)	LDRB_imm_T1

# A8.8.70 LDRB (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0101110(Rm:3)(Rn:3)(Rt:3)	LDRB_reg_T1

# A8.8.79 LDRH (immediate, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
10001(imm5:5)(Rn:3)(Rt:3)	LDRH_imm_T1

# A8.8.82 LDRH (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0101101(Rm:3)(Rn:3)(Rt:3)	LDRH_reg_T1

# A8.8.86 LDRSB (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0101011(Rm:3)(Rn:3)(Rt:3)	LDRSB_reg_T1

# A8.8.90 LDRSH (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0101111(Rm:3)(Rn:3)(Rt:3)	LDRSH_reg_T1

# A8.8.94 LSL (immediate)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
00000(imm5:5)(Rm:3)(Rd:3)	{imm5}	LSL_imm_T1

# A8.8.95 LSL (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100000010(Rm:3)(Rdn:3)	LSL_reg_T1

# A8.8.96 LSR (immediate)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
00001(imm5:5)(Rm:3)(Rd:3)	LSR_imm_T1

# A8.8.97 LSR (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100000011(Rm:3)(Rdn:3)	LSR_reg_T1

# A8.8.102 MOV (immediate)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
00100(Rd:3)(imm8:8)	MOV_imm_T1

# A8.8.103 MOV (register, Thumb)
# T1 ARMv6*, ARMv7
01000110D(Rm:4)(Rd:3)	{lnot(D)} {lt(Rm,8)}	MOV_reg_T1a
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
01000110D(Rm:4)(Rd:3)	{lor(D,ge(Rm,8))}	MOV_reg_T1b
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0000000000(Rm:3)(Rd:3)	MOV_reg_T2

# A8.8.114 MUL
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100001101(Rn:3)(Rdm:3)	MUL_T1

# A8.8.116 MVN (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100001111(Rm:3)(Rd:3)	MVN_reg_T1

# A8.8.119 NOP
# T1 ARMv6T2, ARMv7
1011111100000000	NOP_T1

# A8.8.123 ORR (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100001100(Rm:3)(Rdn:3)	ORR_reg_T1

# A8.8.131 POP (Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
1011110P(reglist:8)	POP_T1

# A8.8.133 PUSH
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
1011010M(reglist:8)	PUSH_T1

# A8.8.145 REV
# T1 ARMv6*, ARMv7
1011101000(Rm:3)(Rd:3)	REV_T1

# A8.8.146 REV16
# T1 ARMv6*, ARMv7
1011101001(Rm:3)(Rd:3)	REV16_T1

# A8.8.147 REVSH
# T1 ARMv6*, ARMv7
1011101011(Rm:3)(Rd:3)	REVSH_T1

# A8.8.150 ROR (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100000111(Rm:3)(Rdn:3)	ROR_reg_T1

# A8.8.152 RSB (immediate)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100001001(Rn:3)(Rd:3)	RSB_imm_T1

# A8.8.162 SBC (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100000110(Rm:3)(Rdn:3)	SBC_reg_T1

# A8.8.167 SETEND
# T1 ARMv6*, ARMv7
10110110010(1)E(000)	SETEND_T1

# A8.8.168 SEV
# T1 ARMv7
1011111101000000	SEV_T1

# A8.8.203 STR (immediate, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
01100(imm5:5)(Rn:3)(Rt:3)	STR_imm_T1
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
10010(Rt:3)(imm8:8)	STR_imm_T2

# A8.8.205 STR (register)
# T1 ARMv4T, ARMv5T*, ARMv6, ARMv7
0101000(Rm:3)(Rn:3)(Rt:3)	STR_reg_T1

# A8.8.206 STRB (immediate, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
01110(imm5:5)(Rn:3)(Rt:3)	STRB_imm_T1

# A8.8.208 STRB (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0101010(Rm:3)(Rn:3)(Rt:3)	STRB_reg_T1

# A8.8.216 STRH (immediate, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
10000(imm5:5)(Rn:3)(Rt:3)	STRH_imm_T1

# A8.8.218 STRH (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0101001(Rm:3)(Rn:3)(Rt:3)	STRH_reg_T1

# A8.8.221 SUB (immediate, Thumb)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0001111(imm3:3)(Rn:3)(Rd:3)	SUB_imm_T1
# T2 ARMv4T, ARMv5T*, ARMv6*, ARMv7
00111(Rdn:3)(imm8:8)	SUB_imm_T2

# A8.8.223 SUB (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0001101(Rm:3)(Rn:3)(Rd:3)	SUB_reg_T1

# A8.8.225 SUB (SP minus immediate)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
101100001(imm7:7)	SUB_sp_imm_T1

# A8.8.228 SVC (previously SWI)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
11011111(imm8:8)	SVC_T1

# A8.8.233 SXTB
# T1 ARMv6*, ARMv7
1011001001(Rm:3)(Rd:3)	SXTB_T1

# A8.8.235 SXTH
# T1 ARMv6*, ARMv7
1011001000(Rm:3)(Rd:3)	SXTH_T1

# A8.8.241 TST (register)
# T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
0100001000(Rm:3)(Rn:3)	TST_reg_T1

# A8.8.247 UDF
# T1 ARMv47, ARMv5T*, ARMv6, ARMv7
11011110(imm8:8)	UDF_T1

# A8.8.274 UXTB
# T1 ARMv6*, ARMv7
1011001011(Rm:3)(Rd:3)	UXTB_T1

# A8.8.276 UXTH
# T1 ARMv6*, ARMv7
1011001010(Rm:3)(Rd:3)	UXTH_T1

# A8.8.424 WFE
# T1 ARMv7
1011111100100000	WFE_T1

# A8.8.425 WFI
# T1 ARMv7
1011111100110000	WFI_T1

# A8.8.426 YIELD
# T1 ARMv7
1011111100010000	YIELD_T1

# B9.3.1 CPS (Thumb)
# T1 ARMv6*, ARMv7
10110110011(im)(0)AIF	CPS_T1
